The present invention relates generally to an integrated circuit having an on-chip current test circuit and, more particularly, to an integrated circuit with an on-chip test circuit for testing quiescent current.
As processors evolve, the number of transistors per unit area of the integrated circuit doubles approximately every two years (Moore's Law), which means that processors are shrinking. As processors shrink, leakage current becomes more significant and less predictable, which can make it difficult when testing integrated circuits to discriminate between properly operating circuitry with naturally high leakage current and defective circuitry that should have naturally low leakage current, but in fact has high leakage due to a fabrication defect.
One known technique for testing integrated circuits for manufacturing faults is Iddq testing, which measures the supply current (also called “quiescent current”), Idd, when the circuit is not switching (i.e., is unclocked) and the inputs are held at substantially constant values.
An alternative technique for testing integrated circuits is scan testing, which involves connecting circuit elements like flip-flops or latches into chains (replacing the latches/flip-flops by scan cells) and supplying test vectors, generated by Automatic Test Pattern Generation (ATPG) software, to the system using a test controller via a test interface. The states of the device under test can then be controlled and observed, by reading digital pins, to detect manufacturing defects. Generation of the test patterns requires a detailed knowledge of the underlying integrated circuit design and due to design and logic layouts there are typically areas of an integrated circuit that cannot be tested via scan testing, which can lead to an integrated circuit passing production tests but failing in customer applications.
Iddq testing is useful because it allows an integrated circuit to be checked for numerous possible faults simply by measuring the leakage current. A small set of test vectors is required to perform the Iddq test because exposing a defect via leakage current can depend upon whether gates are set to 0 or 1 at the time the measurement is made. Iddq tests allow for simple test generation due to a small set of test vectors being required relative to scan testing and can be effective in identifying a range of circuit defects with a low circuit area and design time overhead.
Iddq testing is conventionally performed using an ammeter and expensive automatic test equipment. There is a problem with Iddq testing in that it requires current measurements, which typically involve waiting for a long time (relative to the time taken to read digital pins in scan testing) to let the integrated circuit enter into a quiescent state and the Idd current settle before performing the measurements. This current-settling time can also give rise to test inaccuracy in test results due to noise. Thus, it would be advantageous to have an efficient way to perform Iddq testing.